Computer Architecture
Teaching Staff: Stefanidakis Michael
Course Code: HY-500
Course Type: Core Course
Course Level: Undergraduate
Course Language: Greek
Semester: 3rd
ECTS: 6
Teaching Units: 4
Lecture Hours: 2
Lab/Tutorial Hours: 2L
Total Hours: 4
E Class Page: http://e-class.ionio.gr/courses/DCS114
Short Description:
Introduction to computer architecture. Digital logic, combinatorial and sequential logical circuits. Instruction set architectures. Instruction types, machine cycle and instruction execution. CISC and RISC architectures. Central Processing Unit (CPU). Performance and benchmarking. Instruction level parallelism and pipelining. Superscalar and VLIW processors. Main memory technologies. Memory hierarchies and cache memories. Virtual memory. Input-Output devices, buses and controllers. Interrupts and DMA techniques.
eclass:http://e-class.ionio.gr/courses/DCS114
Module webpage:http://mixstef.github.io/courses/comparch
Suggested Bibliography:
- D.A.Patterson & J.L.Hennessy, Computer Organization and Design, Fourth Edition, Morgan Kaufmann, 2011.
- W. Stallings, Computer Organization and Architecture (9th Edition), Pearson, 2012
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Studies
Secretery Building (Building 3)
7 Tsirigoni Square
Corfu, 49100
tel:26610 87760 / 87761 / 87763
e-mail: cs@ionio.gr
e-mail: cs@ionio.gr
